Read Only Memory (ROM) devices are non-volatile memory devices, thus information and data stored therein will not be lost when power supplies are shut off. Erasable and Programmable Read Only Memory (EPROM) devices have expanded applications of the ROM devices to achieve an erase operation and a re-write operation. However, ultraviolet rays are required to achieve the erase operation, thus manufacturing costs of the EPROM devices are high. Furthermore, when implementing an erase operation to revise data, all programs or data stored in the EPROM device will be erased. Thus, after the erase operation, the EPROM device should be reprogrammed which is time-consuming.
Electrically Erasable and Programmable Read Only Memory (EEPROM) devices can achieve erase operations without above recited deficiencies of the EPROM devices. When erasing data from or re-writing data into an EEPROM device, the erase operation or the re-write operation can be implemented in a manner of one storage unit by another. Therefore, data can be stored into, read out from or eased from the memory devices for more than one time.
Referring to FIG. 1, an existing EEPROM device is illustrated. The EEPROM device includes: a semiconductor substrate 200; an erase gate 201 disposed on a first portion of the semiconductor substrate 200; two float gate dielectric layers 202 disposed on a second and a third portion of the semiconductor substrate 200 respectively, wherein the first portion is between the second portion and the third portion; two float gates 203 respectively disposed on the float gate dielectric layers 202; two control gate dielectric layers 204 respectively disposed on the float gates 203; two control gates 205 respectively disposed on the control gate dielectric layers 204; a tunneling oxide layer 206 disposed between the word line 201 and a first sidewall formed by the float gates 203 and the control gates 205, a spacer 210 disposed on a second sidewall formed by the float gates 203 and the control gates 205; a selecting dielectric layer 207 disposed beside the spacer 210; a selecting gate disposed on the selecting dielectric layer 207; a first doping region 209 disposed beside the selecting gate 208; and a second doping region 211 disposed under the erase gate 201.
Accordingly, in existing EEPROM devices, dimensions (specifically, the widths) of the erase gate and the float gate are substantially the same, thus an area of the contact surface therebetween is fixed. Therefore, a coupling ratio of the float gate to the control gate is limited. As a result, efficiency and stability of the EEPROM device during the erase operation may be reduced, that is, erasing performance of the EEPROM device is not satisfactory.
Furthermore, when implementing an erasing operation to the EEPROM device, all float gates disposed along the same line with the erasing gate will be erased. In other words, each float gate can not be erased separately.
Therefore, erasing performance of the existing EEPROM devices needs to be improved. Furthermore, an EEPROM device whose float gates can be separately erased is demanded.